1. Field of Invention
The present invention generally relates to semiconductor devices, and particularly relates to input/output interfaces of semiconductor devices.
2. Description of Related Art
In semiconductor devices, it is desirable to use high-frequency signals in data input/output so as to achieve high-speed operations. As frequencies of data input/output signals are raised with an aim of achieving high speed operations, however, various factors impeding an effort to raise the frequencies surface. It is required to eliminate these factors one by one.
One of the major factors limiting frequencies of data input/output signals is a signal skew, i.e., a displacement in a signal timing. When an input clock signal for signal synchronization has a skew relative to other signals, for example, it is possible that wrong signals are detected because of timing displacements when the clock signal is used for detecting the other signals. This possibility increases as a signal frequency becomes higher. Because of this, it is difficult to raise the operation speed by increasing the data-input/output signal frequency when a skew is existent between signals.
Causes of such inter-signal skews include a gap in signal timings which is created by differences in signal-path lengths. When a length of each signal line differs from each other, a timing of signal arrival at a receiver chip varies from signal to signal when a plurality of signals are transmitted from a given chip to the receiver chip. Even when the lengths of signal lines are the same, load factors such as path capacitances and path inductances are different between signal lines if these signal lines are laid out on different paths. Differences in such load factors result in differences in signal propagation speed. In this case, thus, signals receives at the receiver side end up containing skews.
Such signal skews do not surface as problems as long as signal frequencies are within a frequency range typically used in conventional DRAMs since such frequency range provides sufficient timing margins for detecting input data. As signal frequencies are raised to exceed about 200 MHz, however, inter-signal skews becomes significant in comparison with a timing margin to detect input data, and, thus, cannot be ignored anymore. This poses a limitation on how much the operation speed can be enhanced.
Accordingly, there is a need for a circuit which can reduce inter-signal skews.